Thesis
On the efficient implementation of the Line Hough Transform for embedded vision systems
- Creator
- Rights statement
- Awarding institution
- University of Strathclyde
- Date of award
- 2023
- Thesis identifier
- T16685
- Person Identifier (Local)
- 201578477
- Qualification Level
- Qualification Name
- Department, School or Faculty
- Abstract
- Many embedded applications increasingly employ computer vision systems to perform visual inspection tasks. Vision systems allow a computer to see and interpret its environment to automate procedures using image processing algorithms. An emerging challenge for modern vision systems is to meet the processing demands of larger image resolutions and higher video frame rates. Field Programmable Gate Arrays (FPGAs) are commonly selected to accelerate embedded vision algorithms as they are widely available, cost-effective, reprogrammable, and energy efficient. They also offer parallel processing capabilities that accelerate algorithms and tasks to achieve low latency processing and high data throughput. Line detection in digital images is essential for many embedded applications, such as lane detection in Advanced Driver Assistance Systems (ADAS) or powerline and railroad inspection using Unmanned Aerial Vehicles (UAVs). The Line Hough Transform (LHT) is a well-known technique for accurately detecting lines in digital images. The LHT achieves line detection by mapping edge pixels to a discrete array known as the Hough Parameter Space (HPS). Peaks form in the HPS that correspond to lines in the original image. Although the LHT is very robust to noise and can detect partially occluded lines, it is also highly computational and demands significant memory resources to store the HPS. Previous studies describe software optimisations to reduce the complexity of the LHT and present FPGA architectures that accelerate its computation. In many FPGA implementations, the memory consumption of the HPS is significant, making the LHT unsuitable for memory-constrained FPGA designs. Large image resolutions, such as 1920 × 1080 pixels, exacerbate this issue, demanding considerable memory resources to store the HPS. This thesis examines the memory consumption of the LHT algorithm in FPGAs and presents a novel research platform for LHT architectures named the Hough Evaluation Platform (HEP). The HEP can be used to design custom LHT architectures and validate them on the physical target device. This powerful validation technique improves the testing of hardware architectures beyond software simulations. The HEP can also accurately calculate the time taken for an LHT architecture to process a digital image. Furthermore, this thesis presents two novel techniques to reduce the memory requirements of the LHT, which are named the Symmetric LHT and the Angular Regions LHT (ARLHT). The FPGA architectures presented for each technique target Full High Definition (FHD) video, i.e. a resolution of 1920×1080 pixels at 60 frames per second (fps). The Symmetric LHT uses architectural optimisations to reduce the memory consumption of the HPS in FPGA devices. The proposed design employs memory bit-packing schemes to reduce on-chip memory resources by approximately 33% without affecting the accuracy of line detection. The ARLHT decreases the memory consumption of the LHT by using a lossy compression scheme to store the HPS. This scheme compresses the HPS by dividing the input image into angular regions before applying the LHT. The ARLHT architecture requires approximately 53% fewer memory resources than the standard LHT.
- Advisor / supervisor
- Murray, Paul
- Crockett, Louise H. (Louise Helen)
- Resource Type
- DOI
Relazioni
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PDF of thesis T16685 | 2023-08-30 | Pubblico | Scaricare |