Thesis

Development of low-cost field-programmable gate array based time-to-digital converters for time-resolved measurements

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Awarding institution
  • University of Strathclyde
Date of award
  • 2024
Thesis identifier
  • T17120
Person Identifier (Local)
  • 202075123
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Abstract
  • Time-to-digital converters (TDCs) are high-precision stopwatches that convert a time interval (TI) into a digital code. They measure TIs with resolutions from nanoseconds (ns) to femtoseconds (fs). Due to their high resolutions, they are key components in time-of-flight (ToF) applications such as light detection and ranging (LiDAR) and positron emission tomography (PET). They are also used in fluorescence lifetime imaging microscopy (FLIM), quantum random number generation (QRNG), highenergy physics, etc. For digital TDCs, both field programmable gate array (FPGA)-TDCs and applicationspecific integrated circuit (ASIC)-TDCs are capable of achieving picosecond (ps)-level resolutions, benefiting from advances in complementary metal-oxide semiconductor (CMOS) manufacturing technologies. However, FPGA-TDCs have shorter developing cycles and lower developing costs than ASIC-TDCs. Hence, FPGA-TDCs are more appropriate for rapid prototype verification. FPGA-TDCs are usually composed of coarse and fine counters to achieve a wide measurement range and high resolution simultaneously. A coarse counter can be easily implemented using a clock-driven counter. Hence, most research focuses on the architecture and calibration methods for fine-time measurements. For a fine counter, the primary parameter is the resolution (also known as the least significant bit, LSB). It is the minimal TI that can be detected. Ideally, all time bins in a TDC should have the same bin width. However, they are not uniform due to the imperfect CMOS manufacturing and clock skews. The variations of bin widths are characterised by differential nonlinearity (DNL) and integral nonlinearity (INL). Besides, measurement results fluctuate for a fixed TI due to jitters and quantization errors. Hence, precision or root-mean-square (RMS) precision is also a parameter of concern for TDCs. This thesis proposes four innovative FPGA-TDCs with novel architectures and calibration methods, aiming to enhance TDCs’ resolution, linearity and hardware utilisation efficiency. The first design proposes an automatic calibration architecture implemented in a Zynq-7000 system on chip (SoC). This design uses the programmable logic (PL) in the SoC to build a 16-channel TDC and uses the processing system (PS) to calibrate all TDC channels in the PL. This TDC offers a resolution of 9.83 ps with good uniformity, achieving an averaged peak-to-peak DNL (DNLpk-pk) of 0.38 LSB and an averaged peak-to-peak INL (INLpk-pk) of 0.63 LSB. The second design proposes several new methods and architectures, with the sampling matrix architecture being the most significant contribution, dramatically enhancing the resolution of the Gray-code oscillator (GCO)-TDC with low hardware utilisation. Besides, the virtual bin calibration method is also proposed and hardware-implemented, aiming at high linearity and variable resolutions. With these innovations, this design can offer a 20.97~80.45 ps resolution with a better than 0.18 LSB averaged DNLpk-pk in the 16-channel TDC implemented in a Zynq UltraScale+ MPSoC. Simultaneously, each channel only uses 456 look-up tables (LUTs) and 368 D-type flip-flops (DFFs), indicating substantial potential for multi-channel applications. Moreover, this design is also implemented in Kintex-UltraScale and Virtex-7 FPGAs, showcasing its universality. The third design combines the wave union (WU) and dual-sampling methods and proposes a bidirectional encoder and a manually-routed WU launcher. The WU launcher generates a four-transition wave pattern to enhance the resolution. The bidirectional encoder is then designed to encode the four transitions in real time. Combined with the sub-tapped-delay line (sub-TDL) method, the proposed TDC implemented in a Zynq UltraScale+ MPSoC achieves a 0.46 ps ultra-high resolution with a 4.44 ns dead time. The fourth design is a two-stage interpolation TDC consisting of a Vernier GCO-TDC (VGCO-TDC) and a TDL-TDC. This architecture uses the TDL-TDC to measure the overtaking residue from the VGCO-TDC. Hence, the TDL-TDC only needs to cover the resolution of the VGCO-TDC, significantly reducing the hardware utilisation of the TDL-TDC. When implemented in a Kintex-UltraScale FPGA, the TDC can achieve an average resolution of 4.57 ps, only consuming 440 LUTs and 570 DFFs. Moreover, this design is also implemented in a Virtex-7 FPGA, showcasing its universality.
Advisor / supervisor
  • Li, David Day-Uei
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DOI
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