Thesis

Run-time reconfigurable systems and algorithms for RFSoC-based software defined radio applications

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Awarding institution
  • University of Strathclyde
Date of award
  • 2026
Thesis identifier
  • T17625
Person Identifier (Local)
  • 201752735
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Qualification Name
Department, School or Faculty
Abstract
  • The growing demand for wireless connectivity has increased the shortage of usable Radio Frequency (RF) spectrum, resulting in congested unlicensed bands and underutilised licensed spectrum. Dynamic Spectrum Access (DSA), enabled by Software Defined Radio (SDR) and Cognitive Radio (CR), shows promise in improving spectrum utilisation by allowing opportunistic and adaptable usage of available bands. However, traditional SDR platforms often suffer from complexity, limited reconfigurability, and non-deterministic behaviour due to disparate hardware technologies. This thesis addresses these challenges by developing practical methodologies and efficient algorithms for RF-sampling FPGA-based SDR devices, particularly AMD’s Zynq UltraScale+ RF System-on-Chip (RFSoC). First, a novel design methodology for SDR applications on the RFSoC is presented and used to develop a fully functional transceiver demonstrator, incorporating real-time data inspection and visualisation. The demonstrator provides user-driven software reconfiguration using Model Composer-generated HDL IP cores and integrated within the PYNQ framework. Experimental results demonstrate effective real-time visualisation at rates up to 20 FPS, with notably low FPGA resource utilisation. This work is shown to have had a positive impact on the community, and beyond, serving as a foundation for subsequent research. Second, this research introduces SPECTRE, an open-source, Python-based frequency planning tool designed to dynamically identify spur-free configurations for RFSoCs. Frequency planning is defined as a search space problem and, through analysis, key interference spurs were identified, and various search algorithms evaluated. Results highlight that a hybrid search strategy combining coarse grid and exhaustive random searches could achieve real-time performance on the RFSoC. Finally, a novel FPGA-based fixed-point filter design method is developed for run-time reconfigurable FIR filters. Results show excellent filter performance (up to 88 dB stopband attenuation) and ultra-low deterministic latency (2.52 µs), suitable for real-time SDR applications. All tools developed in this thesis were publicly released as open-source, significantly contributing to practical and accessible SDR and CR applications.
Advisor / supervisor
  • Crockett, Louise H.
  • Stewart, Robert W.
Resource Type
DOI

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