Thesis
Design and implementation of high linearity FPGA-TDCs and an integrated large scale TCSPC system for time-resolved applications
- Creator
- Rights statement
- Awarding institution
- University of Strathclyde
- Date of award
- 2020
- Thesis identifier
- T15632
- Person Identifier (Local)
- 201491805
- Qualification Level
- Qualification Name
- Department, School or Faculty
- Abstract
- The time-correlated single-photon counting (TCSPC) technology is a vital, advanced measurement and analytical tool for time-resolved biomedical, physics research and many industry areas because of its high temporal resolution and sensitivity. Analogue-based conventional TCSPC systems have been commercialised and applied in scientific experiments widely. However, the complicated system of conventional TCSPC equipment causes the bulky size, high cost, low conversion rate and limited channel number. With the recent rapid development of semiconductor technology, Field Programmable Gate Arrays (FPGA) become the promising platforms for high-performance digital TCSPC systems.;The time-to-digital converter (TDC) is the core component of a TCSPC system as it provides the temporal measurements with extremely high-resolution. For the scientific experiments, prototyping and high-end instruments, FPGA-based TDCs or TCSPC systems can provide excellent flexibility and compatibility with the much lower design and implementation costs. However, compared with ASIC and analogue implementations, the reported FPGA-TDCs have poor linearity performances with severe non-linearity problems such as missing-codes, ultra-wide bins and the bubbles problems. As a result, this study focuses on to improve the linearity performance by exploring the sources of non-linearity in the tapped delay line (TDL)-based FPGA-TDCs;This thesis proposes two novel FPGA-TDC designs to address the linearity drawbacks. The first TDC design proposes a combination architecture innovatively to restrain the differential non-linearity (DNL) to < ±1LSB (LSB = 10.5ps) with the complete removal of missing-codes. By developing and using a hardware-friendly bin-width calibration, the DNL has been reduced to < ±0.1LSB. Furthermore, getting benefits from the direct-histogram architecture, the proposed FPGA-TDC/TCSPC design has the capability of multi-event measurement and ultra-low dead-time (<100ps). The second TDC design proposes several new methods and architectures with minimised resource consumption for multiple-channel applications. The most significant contribution of this design is an ideal solution, the sub-TDL topology, for the 'bubble' problems has been proposed and verified. Next, the tap timing test method, which is derived from the sub-TDL topology, can provide more exact timing details compared with the wide-used code density test.;By applying the proposed compensation and calibration method, its linearity can be improved to < ±0.12LSB with 5ps temporal resolution. Two 96-channel TCSPC arrays have been implemented in different FPGA series which demonstrate the excellent potential for multi-channel designs.;Besides, an integrated, large-scale TCSPC array base on a world-leading SPAD sensor and TDC array is presented in this thesis for fast, wide-field, time-resolved applications. The system provides >24K independent TCSPC channels with both photon counting and time-correlated imaging mode and a tunable temporal resolution. For verification, this study applied the system in a typical fluorescence lifetime measurement. According to the CMM calculated results base on the measured data, the proposed system demonstrated the accurate and reliable measurement performances.
- Advisor / supervisor
- Li, David
- McConnel, Gail
- Resource Type
- DOI
- Date Created
- 2020
- Former identifier
- 9912890393102996
Relations
Items
| Thumbnail | Title | Date Uploaded | Visibility | Actions |
|---|---|---|---|---|
|
|
PDF of thesis T15632 | 2021-07-02 | Public | Download |